library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CONV_STD_DIR is
    port(
         clk: in std_logic;
         Xstd: in std_logic;
	 		Ystd: in std_logic_vector(34 downto 0);
	 		Zstd: in std_logic_vector(34 downto 0);
	 		Ydir: out integer range 320 downto 0;
	 		Zdir: out integer range 320 downto 0
   	);
end CONV_STD_DIR;

-- Esto lo unico que hace es esta cuenta (si X>0):
--160+160*Y
--160-160*Z

-- La idea es agarrar el numero, multiplicarlo por 16 y dividirlo por 1.000.000.000

architecture Convertir of CONV_STD_DIR is
begin
    process(clk)
        constant PASOS: integer:= 38;
        constant M: std_logic_vector(37 downto 0):=std_logic_vector(to_unsigned(1000000000,38));
        variable Q: std_logic_vector(37 downto 0);
        variable A: std_logic_vector(37 downto 0);
    begin
      if rising_edge(clk) then
         if Xstd='0' then
            if Ystd(34)='0' then 
               Q:=Ystd(33 downto 0) & "0000";
            else
               Q:=(not(Ystd(33 downto 0))+1) & "0000";
            end if;
            A:=(37 downto 0 =>'0');
            for i in PASOS-1 downto 0 loop
               A:=A(36 downto 0) & Q(37);
               Q:=Q(36 downto 0) & '0';
               if A>=M then
                   Q(0):='1';
                   A:=A-M;
               end if;
            end loop;
            if Ystd(34)='1' then
               Ydir <= 160 - conv_integer(Q(7 downto 0));
            else
               Ydir <= 160 + conv_integer(Q(7 downto 0));
            end if;
            
            if Zstd(34)='0' then 
               Q:=Zstd(33 downto 0) & "0000";
            else
               Q:=(not(Zstd(33 downto 0))+1) & "0000";
             end if;
            A:=(37 downto 0 =>'0');
            for i in PASOS-1 downto 0 loop
               A:=A(36 downto 0) & Q(37);
               Q:=Q(36 downto 0) & '0';
               if A>=M then
                   Q(0):='1';
                   A:=A-M;
               end if;
            end loop;
            if Zstd(34)='1' then
               Zdir <= 160 + conv_integer(Q(37) & Q(7 downto 0));
            else
               Zdir <= 160 - conv_integer(Q(7 downto 0));
            end if;
		   end if;
		end if;
	end process;
end Convertir; 


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity test_cnv is
end test_cnv;

architecture simul of test_cnv is
	component CONV_STD_DIR is
    port(
         clk: in std_logic;
         Xstd: in std_logic;
	 		Ystd: in std_logic_vector(34 downto 0);
	 		Zstd: in std_logic_vector(34 downto 0);
	 		Ydir: out integer range 320 downto 0;
	 		Zdir: out integer range 320 downto 0
   	);
  end component;

	signal clk: std_logic:='0';
	signal Xi : std_logic:='0';
	signal Yi : std_logic_vector (34 downto 0):="00100000011001011101010101000111100"; -- 
	signal Zi : std_logic_vector (34 downto 0):="11011111100110100010101010111000100"; -- 
	signal Yo : integer range 320 downto 0;
	signal Zo : integer range 320 downto 0;
	
	
begin
    
	cnv : CONV_STD_DIR port map (clk,Xi,Yi,Zi,Yo,Zo);
	
clk <= not clk after 10 ns;

end simul;   
        